The invention generally relates to dynamic logic circuits. More particularly, the invention relates to a new family of self-clocked dynamic logic gates.
A static logic gate is a fully complementary logic gate having both PMOS and NMOS devices configured to implement a desired function. Typically, each NMOS device is accompanied by a corresponding PMOS device. In this way, a static CMOS gate is expensive to implement and requires significant die space.
A dynamic logic gate consists of a structure having a single output node and any number of NMOS devices coupled to the output node for conditionally discharging the output node to a low voltage rail Vss depending upon inputs to the NMOS devices. A dynamic logic gate also includes at least one PMOS device which is coupled to the output node for precharging the output node to a high voltage rail Vcc. The PMOS device has a gate coupled to a clock signal, a source coupled to the high voltage rail and a drain coupled to the output node. When the clock signal is low, the PMOS device is turned on and the output node is precharged and driven to the high voltage rail Vcc. When the clock signal is high, the logic gate is evaluated. If the inputs which are coupled to the gates of the NMOS transistors become high, the output node is conditionally discharged (evaluated) through the NMOS devices to the low voltage rail Vss.
A conventional dynamic logic circuit usually includes multiple dynamic logic gates which are arranged in a plurality of stages, wherein the operation of each gate in the unit is controlled by the clock signal and the outputs from the prior stage. In this arrangement, input signals applied to a first stage while the clock signal is active trigger operation of the remaining stages in sequence, yielding a domino-like signal propagation through the conventional dynamic logic circuit. Hence, the term xe2x80x9cdominoxe2x80x9d logic is often used in describing such circuits. In a conventional xe2x80x9cdominoxe2x80x9d logic circuit each of the stages are coupled to the clock signal and are precharged when the clock signal is low.
FIG. 1 illustrates a domino logic circuit having a first stage dynamic AND gate coupled to a second stage NAND gate. The first stage dynamic AND gate is designated by the broken lines 100 and the second stage dynamic NAND gate is designated by the broken lines 200 in FIG. 1. The first stage dynamic AND gate 100 includes a PMOS transistor 110 having a gate coupled to a clock signal CLK, a source coupled to a high voltage rail VDD, and a drain coupled to an output node 120. The drain of the PMOS transistor 110 is also coupled to a drain of first NMOS transistor 130. A gate of the first NMOS transistor 130 is coupled to receive an input signal A and a source of first NMOS transistor 130 is coupled to a drain of a second NMOS transistor 140. A gate of the second NMOS transistor 140 is coupled to receive an input signal B and a source of the second NMOS transistor 140 is coupled to a drain of a third NMOS transistor 150. A gate of the third NMOS transistor 150 is coupled to receive the clock signal CLK and a source of the third NMOS transistor 150 is coupled to a low voltage rail Vss. The output node 120 is coupled to an input of an inverter 160, having an output O1. The output O1 is the output from the first stage dynamic AND gate 100.
In operation, when the clock signal CLK is inactive (low), then the PMOS transistor 110 is on and the third NMOS transistor 150 is off. In this state, the output node 120 is precharged to the high voltage rail VDD and the output O1 of the inverter 160 is driven low. Accordingly, the output O1 from the first stage dynamic AND gate 100 is initially driven low during precharge between each evaluate cycle. When the clock signal goes active (high), the PMOS transistor 110 turns off and the third NMOS transistor 150 turns on. This allows the voltage at the output node 120 to be evaluated or selectively discharged depending upon the inputs A and B. If the voltages at the inputs A and B are both high, then both the first and second NMOS transistors 130 and 140 will turn on. When this occurs, the voltage at the output node 120 drops to the low voltage rail Vss and the output O1 of the inverter 160 is driven high. If only one of the inputs A or B is high, while the other is low, then both the first and second NMOS transistors 130 and 140 will not turn on (only one of the transistors will turn on while the other will remain off), in which case the voltage at the output node 120 will remain at the high voltage rail VDD and the output O1 from the inverter 160 will remain low. Accordingly, only when the voltages at both inputs A and B are both high during the evaluate cycle will the output from the inverter 160 be driven high.
The first stage dynamic AND gate 100 also, optionally, includes a feedback circuit which is designated by the broken lines 170 in FIG. 1. The feedback circuit 170 is comprised of a PMOS transistor 180 having a source coupled to the high voltage rail VDD, a drain coupled to the output node 120, and a gate coupled to the output O1 of the inverter 160. Over time, the precharge voltage at the output node 120 may drop due to leakage of through current which may be caused if noise at the inputs A and B inadvertently activate the NMOS transistors 130 and 140. If the voltage at the output node 120 were to drop below a certain level due to leakage of through current through transistors 130, 140 and 150, this would cause the output O1 at the inverter 160 to change to a xe2x80x9cfalsexe2x80x9d high, thereby effecting the entire circuit. The feedback circuit 170 is used to keep the voltage at the output node 120 stable until the inputs are all valid, thereby ensuring that the voltage at the output O1 of the inverter 160 remains low until the inputs A and B are both high.
As indicated earlier, in the domino logic shown in FIG. 1, a second stage dynamic NAND gate 200 is coupled to the first stage dynamic AND gate 100. The second stage dynamic NAND gate 200 includes a PMOS transistor 210 having a gate coupled to the output of a delay circuit 280, a source coupled to the high voltage rail VDD, and a drain coupled to an output node 220. Typically, the delay circuit 280 is designed to receive the incoming clock signal CLK and delay the falling edge of the incoming clock signal CLK during the precharge phase. The falling edge of the clock signal is delayed a sufficient period of time until the output O1 from the first stage dynamic AND gate 100 is switched low (the output O1 from the first stage dynamic AND gate is switched low once the voltage at node 120 has been sufficiently precharged toward the high voltage rail VDD (thereby activating the inverter 160 and inverting the voltage at the output node O1 back toward the low voltage rail Vss.
The drain of the PMOS transistor 210 is also coupled to a drain of an NMOS transistor 230. A gate of the NMOS transistor 230 is coupled to receive the output O1 from the first stage dynamic AND gate 100 and a source of the NMOS transistor 230 is coupled to a drain of an NMOS transistor 240. A gate of the NMOS transistor 240 is coupled to receive an input signal C and a source of the NMOS transistor 240 is coupled to the low voltage rail. It is noted that the second stage is commonly referred to as a xe2x80x9cfootlessxe2x80x9d dynamic logic circuit since no additional clock controlled NMOS transistor is utilized during the evaluate cycle.
During the precharge stage, the delayed clock signal CLKxe2x80x2 is inactive and, the PMOS transistor 210 is active, thereby precharging the voltage at node 120 to the high voltage rail VDD. During evaluation, if the output O1 from the first stage AND gate 100 is high and the input C to the second stage NAND gate 200 is also high, then both NMOS transistors 230 and 240 turn on. When this occurs the voltage at the output node 220 drops to the low voltage rail Vss. However, if during evaluation only one of either the output O1 from the first stage AND gate 100 or the input C is high, while the other is low, then both NMOS transistors 230 and 240 will not turn on (only one of the transistors will turn on while the other will remain off), in which case the voltage at the output node 220 will remain at the high voltage rail VDD. Accordingly, only when the output O1 from the first stage AND gate 100 and the input C are both high will the output O2 from the second stage NAND gate 200 be driven low during the evaluation stage, in all other cases it will remain high during the evaluation stage.
As can be seen from the conventional domino logic circuit shown in FIG. 1, implementation of traditional dynamic xe2x80x9cdominoxe2x80x9d logic circuitry poses several problems. First, the falling edge of the clock signal CLK must be delayed during the precharge phase, in order to save power by cutting down through current. If the clock signal CLK is not delayed then wasted through current may occur. If the falling edge of the clock signal were not delayed and the clock signal was coupled directly to the gate of transistor 210 in the second stage NAND gate 200, then when the clock signal CLK went low the transistor 210 would turn on. This might occur before node 120 is sufficiently precharged to activate inverter 160. Accordingly, if the output O1 from the first stage AND gate 100 was previously high, it will remain high until the node 120 is fully precharged. If the input C is also driven high before node 120 is fully precharged then there will be a current path from Vdd to Vss through transistors 210, 230 and 240. This is a waste of current and power. This may occur until the output O1 from the first stage CMOS AND gate 100 is driven low once node 120 is sufficiently precharged and inverter 160 is activated. Accordingly, the delay logic is needed to delay the falling edge of the delayed clock signal CLKxe2x80x2 until the output O1 from the first stage CMOS AND gate 100 is switched low during precharge.
The amount of delay required may vary from circuit to circuit and must be custom designed to meet specific circuit characteristics. This adds increased costs to the manufacture of most domino logic families. Moreover, because performance characteristics may vary over time, these customized delay circuits may not always operate reliably (i.e., the delay associated with the delay circuit may vary over time as operating conditions change). Accordingly, what is needed is a new dynamic logic circuit wherein subsequent stages in the circuit design are not dependent upon a delayed clock signal for precharging so there is no need to custom design delay circuits between stages.
Additionally, the amount of power required to drive a circuit having multiple stages is proportional to the load capacitance and the switching frequency of each stage in the circuit. Because each stage in a conventional domino logic circuit is connected to the clock signal (which has the highest frequency of any signal in the circuit) in order to precharge the output from that stage during the precharge phase, as the number of stages increases the load capacitance seen by the clock signal increases and the circuit design requires increased power in order to operate. Accordingly, what is needed is a circuit design which has a lower load capacitance seen by the clock signal and which does not require each stage to be coupled to a clock signal for prechargingxe2x80x94i.e. where the precharging of each stage is not dependent upon any clock signal.
A major concern when it comes to dynamic logic circuit design is noise. For example, if the outputs from a first stage in a conventional domino logic design transmit noise and are used as inputs to a next stage, the output from the next stage may inadvertently be erroneously discharged before the actual inputs to any stage are actually valid. One traditional way of minimizing this effect between stages is to shield the coupling between stages or buffer the inputs/outputs between stages using a pair of static CMOS inverters. However, this increases overall manufacturing and production costs. Moreover, buffering the inputs and outputs between stages results in additional delay time as the signal passes through the buffer, which, in turn, causes the chip to operate at a lower frequency. Accordingly, what is needed is a new dynamic logic family which is able to perform reliably even in the presence of significant noise at the output/inputs between stages and does not suffer the speed loss as in the case of using a buffer at each of the inputs/outputs.
The invention is for a new self clocking family of dynamic logic gates which replace footless or subsequent stage dynamic logic gates in multi-stage domino logic circuit.
In one embodiment of the present invention, a multiple stage logic circuit is designed having a first stage which utilizes a traditional dynamic logic gate design and a second stage which includes a new self-clocking dynamic logic gate design. The output from the first stage is coupled to the input of the second stage such that the second stage is not dependent upon any type of clock signal for precharging. Instead, the second stage includes a new self clocking dynamic logic gate design which utilizes a dual transistor arrangement on the inter-stage inputs (i.e. the outputs from one stage which are input to subsequent stages) in order to precharge the output node at the second stage such that no delayed clock signal is needed during precharge.
Accordingly, the output from the second stage which is designed in accordance with the new family of self-clocking dynamic logic gates is efficiently precharged without using a delayed clock signal or any customized delay circuitry while minimizing through current by design. This allows the multi-stage domino logic circuit to be designed with lower power consumption since through current is minimized by design. Instead of using a delayed clock signal in precharge between stages. The output from the previous stage is used to activate the subsequent stage in both precharge and evaluate. Each self-clocking dynamic logic gate designed in accordance with the present invention includes an NMOS and PMOS transistor pair which each share a common output node. By coupling the output from the previous stage to the gates of both the PMOS and NMOs device, one may be activated during precharge while the other is deactivated. Thereby inhibiting any direct path to the low voltage rail Vss and reducing through current by design.
In a second embodiment of the present invention, a multiple stage domino logic circuit is designed having a first stage which utilizes a traditional dynamic logic gate design and a second stage which utilizes a new self clocking dynamic logic gate design which is not dependent upon any delayed clock signal. The second stage further includes a noise/leakage circuit at each of the inputs. The noise/leakage circuit is designed to ensure a stable and accurate output from the new self-clocking dynamic logic circuit until the inputs to that stage are valid. The noise/leakage circuit also protects against any improper operation which may be caused by any noise on the input lines.
In a third embodiment of the present invention, multiple self-clocking dynamic logic gates may be implemented within a single domino logic circuit design with their individual outputs summed in order to perform any desired combinational logic circuitry function.